Integrated circuit development in the semiconductor industry is guided by the precept that the number of transistors per unit area of a die will increase generation after generation. Today, the number of transistors per die is typically on the order of billions. This staggering number has been achieved by scaling down the physical dimensions of transistors to allow more transistors to be fit per unit area of the die. By increasing the number of transistors, more elaborate circuits may be made to increase the functionality of microprocessors.
Currently, transistors are fabricated during front-end-of-line (FEOL) manufacturing processes. More particularly, the transistor structure is fashioned onto the semiconductor material of the die itself, i.e., in an FEOL portion of the die. For example, a gate, source, and drain of each transistor is built along a planar surface of the semiconductor material of the die. The die also includes a back-end-of-line (BEOL) portion having interconnects between the FEOL transistors and an external interface of the die, such as a bonding pad.
The FEOL portion and the BEOL portion of the die may be distinguished from each other in several ways. First, the FEOL portion may be fabricated in an FEOL manufacturing process having a higher thermal budget than a BEOL manufacturing process used to fabricate the BEOL portion. For example, the FEOL manufacturing process may have a thermal budget on an order of thousands of degrees Celsius, e.g., 1000° C., and the BEOL manufacturing process may have a thermal budget on an order of hundreds of degrees Celsius, e.g., 400° C. Second, the FEOL portion typically includes active components, e.g., transistors, and the BEOL portion typically includes passive components, e.g., electrical interconnects and vias.